Table of Contents
Advertisement
TMW—Timer Mode Register W
Note: This register is implemented on the H8/38124 Group only.
Bit
7
Initial value
1
Read/Write
Rev. 6.00, 08/04, page 592 of 628
6
5
1
1
Internal Clock Select
CDS3
CDS2
CDS1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
*
*
0
Note: Valid when WDCKS bit in PMR2 register is cleared to 0.
H'F8
4
3
2
CKS3
CKS2
1
1
1
R/W
R/W
CDS0
Clock source
φ/64
0
φ/128
1
φ/256
0
φ/512
1
φ/1024
0
φ/2048
1
φ/4096
0
φ/8192
1
*
On-chip oscillator
Watchdog Timer
1
0
CKS1
CKS0
1
1
R/W
R/W
Advertisement
Table of Contents
