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CKSTPR2—Clock Stop Register 2
Bit
7
LVDCKSTP*
Initial value
1
Read/Write
R/W
LVD Module Standby Mode Control
0 LVD is set to module standby mode
1
LVD module standby mode is cleared
Note: * Control using the LVDCKST bit is implemented on the H8/38124 Group only.
6
5
1
1
WDT Module Standby Mode Control
0 WDT is set to module standby mode
1
Asynchronous Event Counter Module Standby Mode Control
0 Asynchronous event counter is set to module standby mode
1
Asynchronous event counter module standby mode is cleared
PWM2 Module Standby Mode Control
0 PWM2 is set to module standby mode
1
PWM2 module standby mode is cleared
H'FB
4
3
PW2CKSTP
AECKSTP
WDCKSTP
1
1
R/W
R/W
LCD Module Standby Mode Control
0 LCD is set to module standby mode
1
LCD module standby mode is cleared
PWM1 Module Standby Mode Control
0 PWM1 is set to module standby mode
1
PWM1 module standby mode is cleared
WDT module standby mode is cleared
Rev. 6.00, 08/04, page 595 of 628
System Control
2
1
PW1CKSTP
LDCKSTP
1
1
R/W
R/W
R/W
0
1
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