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An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
However, the procedure in Figure 3.7 is recommended because IECPWM is an internal signal and
determining its value is complicated.
CCR I bit
Set port mode register (or AEGSR) bit
Execute NOP instruction
Clear interrupt request flag to 0
CCR I bit
Figure 3.7 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag
3.4.3
Method for Clearing Interrupt Request Flags
Use the recommended method, given below when clearing the flags of interrupt request registers
(IRR1, IRR2, IWPR).
• Recommended method
Use a single instruction to clear flags. The bit control instruction and byte-size data transfer
instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 of IRR1) are
given below.
BCLR
#1,
@IRR1:8
MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101)
• Example of a malfunction
When flags are cleared with multiple instructions, other flags might be cleared during
execution of the instructions, even though they are currently set, and this will cause a
malfunction.
Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1
(bit 1 of IRR1).
Rev. 6.00, 08/04, page 98 of 628
←
1
←
0
Clearing Procedure
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
After setting the port mode register
(or AEGSR) bit, first execute at least
one instruction (e.g., NOP), then clear
the interrupt request flag to 0
Interrupt mask cleared
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