Renesas H8/38024 Hardware Manual page 113

Bits 4 and 3—IRQ
4
Bit n
IRRIn Description
0 Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
Bit 2—IRQAEC Interrupt Request Flag (IRREC2)
Bit 2
IRREC2 Description
0 Clearing conditions:
When IRREC2 = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQAEC is designated for interrupt input and the designated signal edge is
input
Bits 1 and 0—IRQ
1
Bit n
IRRIn Description
0 Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
and IRQ Interrupt Request Flags (IRRI4 and IRRI3)
3
and IRQ Interrupt Request Flags (IRRI1 and IRRI0)
0
(initial value)
(initial value)
(initial value)
Rev. 6.00, 08/04, page 83 of 628
(n = 4 or 3)
(n = 1 or 0)