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Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
Description
0
Disables asynchronous event counter interrupt requests
1
Enables asynchronous event counter interrupt requests
For details of SCI3 interrupt control, see section 10.2.6 Serial control register 3 (SCR3).
Interrupt Request Register 1 (IRR1)
Bit
IRRTA
Initial value
R/(W) *
Read/Write
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
IRQAEC, IRQ
, IRQ
4
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7—Timer A Interrupt Request Flag (IRRTA)
Bit 7
IRRTA
Description
0
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
1
Setting conditions:
When the timer A counter value overflows from H'FF to H'00
Bit 6—Reserved
Bit 6 is reserved; it can only be written with 0.
Bit 5—Reserved
Bit 5 is reserved; it is always read as 1 and cannot be modified.
Rev. 6.00, 08/04, page 82 of 628
7
6
5
0
1
W
, IRQ
, or IRQ
interrupt is requested. The flags are not cleared
3
1
0
4
3
IRRI4
IRRI3
IRREC2
0
0
R/(W) *
R/(W) *
R/(W) *
(initial value)
2
1
0
IRRI1
IRRI0
0
0
0
R/(W) *
R/(W) *
(initial value)
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