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SYSCR1—System Control Register 1
Bit
7
SSBY
Initial value
0
Read/Write
R/W
Software Standby
0 • When a SLEEP instruction is executed in active mode, a transition is
1
Notes: 1. Applies to products other than the H8/38124 Group.
2. Applies to the H8/38124 Group.
Rev. 6.00, 08/04, page 584 of 628
6
5
STS2
STS1
0
0
R/W
R/W
Standby Timer Select 2 to 0
Wait time = 8,192 states *
0
0 0
Wait time = 16,384 states *
1
Wait time = 1,024 states *
1 0
Wait time = 2,048 states *
1
Wait time = 4,096 states *
0 0
1
Wait time = 2 states *
1
Wait time = 8 states *
1 0
Wait time = 16 states *
1
made to sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
• When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode
H'F0
4
3
STS0
LSON
0
0
R/W
R/W
Low Speed on Flag
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ
Wait time = 8,192 states *
1
Wait time = 16,384 states *
1
Wait time = 32,768 states *
1
Wait time = 65,536 states *
1
Wait time = 131,072 states *
1
Wait time = 2 states *
1
Wait time = 8 states *
1
Wait time = 16 states *
1
System Control
2
1
0
MA1
MA0
1
1
1
R/W
R/W
Active (medium-speed)
Mode Clock Select
φ
0
0
/16
osc
φ
1
/32
osc
φ
/64
1
0
osc
φ
/128
1
osc
SUB
2
2
2
)
2
2
2
2
2
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