Renesas H8/38024 Hardware Manual page 558

Instruction Mnemonic
BTST BTST Rn, @aa:8
BXOR BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
CMP CMP. B #xx:8, Rd
CMP. B Rs, Rd
CMP.W Rs, Rd
DAA DAA.B Rd
DAS DAS.B Rd
DEC DEC.B Rd
DIVXU DIVXU.B Rs, Rd
EEPMOV EEPMOV
INC INC.B Rd
JMP JMP @Rn
JMP @aa:16
JMP @@aa:8
JSR JSR @Rn
JSR @aa:16
JSR @@aa:8
LDC LDC #xx:8, CCR
LDC Rs, CCR
MOV MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @Rs, Rd
MOV.B @(d:16, Rs), Rd
MOV.B @Rs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @–Rd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
Note: * n: Initial value in R4L. The source and destination operands are accessed n + 1 times each.
Internal operation N is 0 for HD64F38024, HD64F38024F, H8/38024S Group and H8/38124 Group.
Rev. 6.00, 08/04, page 528 of 628
Instruction Branch
Fetch Addr. Read
I J
2
1
2
2
1
1
1
1
1
1
1
2
1
2
2
2 1
2
2
2 1
1
1
1
1
1
2
1
1
2
1
2
1
1
2
2
1
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2
Stack Byte Data
Operation Access
K L
1
1
1
2n+2 *
1
1
1
1
1
1
1
1
1
1
1
1
1
Word Data Internal
Access Operation
M N
12
1 *
2
2
2
2
2
1
1
1 2
1