Renesas H8/38024 Hardware Manual page 179

Figure 6.5 shows a PROM write/verify timing diagram.
Address
t
AS
Data
t
DS
V
PP
V
PP
V t
CC VPS
CC +1
V
V
CC
t
V
VCS
CC
CE
t
CES
PGM
OE
Note: * t
is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
OPW
Write
Input data
t
DH
t
PW
*
t
OPW
Figure 6.5 PROM Write/Verify Timing
t t
OES OE
Rev. 6.00, 08/04, page 149 of 628
Verify
t
AH
Output data
t
DF