Renesas H8/38024 Hardware Manual page 197

Write pulse application subroutine
Apply Write Pulse
WDT enable
Set PSU bit in FLMCR1
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time = programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
Disable WDT
End Sub
Figure 6.10 Program/Program-Verify Flowchart
Set SWE bit in FLMCR1
Store 128-byte program data in program
data area and reprogram data area
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Apply Write pulse
Set PV bit in FLMCR1
Set block start address as
verify address
H'FF dummy write to verify address
Read verify data
Verify data =
Increment address
write data?
Yes
Additional-programming data
computation
Reprogram data computation
No
data verification
completed?
Clear PV bit in FLMCR1
Successively write 128-byte data from
additional-programming data area
in RAM to flash memory
Apply Write Pulse
Clear SWE bit in FLMCR1
Wait 100 µs
End of programming
START
Wait 1 µs
n = 1
m = 0
Wait 4 µs
Wait 2 µs
No
m = 1
Yes
No
n ≤ 6 ?
128-byte
Yes
Wait 2 µs
No
n ≤ 6?
Yes
Sub-Routine-Call
No
m = 0 ?
Yes
Clear SWE bit in FLMCR1
Rev. 6.00, 08/04, page 167 of 628
n ← n + 1
Yes
n ≤ 1000 ?
No
Wait 100 µs
Programming failure