Renesas H8/38024 Hardware Manual page 551

8-bit single-chip microcomputer h8 family/h8/300l super low power series
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Mnemonic
BIOR #xx:3, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
BIXOR #xx:3, Rd
BIXOR #xx:3, @Rd
BIXOR #xx:3, @aa:8
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
JMP @Rn
JMP @aa:16
JMP @@aa:8
BSR d:8
Branching
Operation
Condition
B C∨(#xx:3 of @aa:8) → C
B C⊕(#xx:3 of Rd8) → C
B C⊕(#xx:3 of @Rd16) → C
B C⊕(#xx:3 of @aa:8) → C
B C⊕(#xx:3 of Rd8) → C
B C⊕(#xx:3 of @Rd16) → C
B C⊕(#xx:3 of @aa:8) → C
 PC ← PC+d:8
 PC ← PC+2
C ∨ Z = 0
If
condition
C ∨ Z = 1
is true
C = 0
then
PC ←
C = 1
PC+d:8
Z = 0
else next;
Z = 1
V = 0
V = 1
N = 0
N = 1
N⊕V = 0
N⊕V = 1
Z ∨ (N⊕V) = 0
Z ∨ (N⊕V) = 1
 PC ← Rn16
 PC ← aa:16
 PC ← @aa:8
 SP−2 → SP
PC → @SP
PC ← PC+d:8
Addressing Mode/
Instruction Length (bytes)
4
2
4
4
2
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
Rev. 6.00, 08/04, page 521 of 628
Condition Code
I H N Z V C
    
6
    
2
    
6
    
6
    
2
    
6
    
6
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
4
     
6
     
8
     
6

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H8/38024f-ztatH8/38124H8/38024s

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