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Bit 0—Asynchronous Event Counter Interrupt Request Flag (IRREC)
Bit 0
IRREC
Description
0
Clearing conditions:
When IRREC = 1, it is cleared by writing 0
1
Setting conditions:
When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit
counter mode
Wakeup Interrupt Request Register (IWPR)
Bit
IWPF7
Initial value
R/(W) *
Read/Write
Note: * Only a write of 0 for flag clearing is possible
IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins
WKP
to WKP
is designated for wakeup input and a rising or falling edge is input at that pin, the
7
0
corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the
corresponding interrupt is accepted. Flags must be cleared by writing 0.
Bits 7 to 0—Wakeup Interrupt Request Flags (IWPF7 to IWPF0)
Bit n
IWPFn
Description
0
Clearing conditions:
When IWPFn= 1, it is cleared by writing 0
1
Setting conditions:
When pin WKP
that pin
Rev. 6.00, 08/04, page 86 of 628
7
6
5
IWPF6
IWPF5
0
0
0
R/(W) *
R/(W) *
is designated for wakeup input and a rising or falling edge is input at
n
4
3
IWPF4
IWPF3
IWPF2
0
0
R/(W) *
R/(W) *
R/(W) *
(initial value)
2
1
0
IWPF1
IWPF0
0
0
0
R/(W) *
R/(W) *
(initial value)
(n = 7 to 0)
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