System Clock And Subclock; Register Descriptions - Renesas H8/38024 Hardware Manual

Internal reset signal (other than watchdog timer or low-voltage detect
circuit reset)
C
D
IRQAEC
Latch
System
OSC
1
clock
OSC
oscillator
2
On-chip
oscillator
X
1
Subclock
oscillator
X
2
Figure 4.2 Block Diagram of Clock Pulse Generators (H8/38124 Group)
4.1.2

System Clock and Subclock

The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φ
of the clock signals have names: φ is the system clock, φ
clock, and φ
is the watch clock.
W
The clock signals available for use by peripheral modules are φ/2, φ/4, φ/8, φ/16, φ/32, φ/64,
φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φ
and φ
/128. The clock requirements differ from one module to another.
W
4.1.3

Register Descriptions

Table 4.1 lists the registers that control the clock pulse generators. The registers listed in table 4.1
are only implemented in the H8/38124 Group.
Table 4.1 Clock Pulse Generator Control Registers
Name
Clock pulse generator control
register
Rev. 6.00, 08/04, page 102 of 628
Q
System
φ
clock
OSC
divider
(f )
OSC
(1/2)
R
OSC
System clock pulse generator
φ
Subclock
W
divider
(f )
W
(1/2, 1/4, 1/8)
Subclock pulse generator
Abbreviation
OSCCR
φ
/2
OSC
φ
System /16
OSC
φ
clock /32
OSC
φ
/64
divider
OSC
φ
/128
OSC
φ
/2
W
φ
/4
W
φ
/8
W
is the subclock, φ
SUB
, φ /2, φ /4, φ
W W W
R/W Initial Value
R/W —
φ
φ /2
Prescaler S
to
(13 bits)
φ /8192
φ
W
φ
SUB
φ
W
φ
W
φ
W
Prescaler W
to
(5 bits) φ
W
. Four
SUB
is the oscillator
OSC
/8, φ /16, φ /32, φ
W W W W
Address
H'FFF5
/2
/4
/8
/128
/64,