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Renesas H8/38124 Series Manuals
Manuals and User Guides for Renesas H8/38124 Series. We have
2
Renesas H8/38124 Series manuals available for free PDF download: Hardware Manual
Renesas H8/38124 Series Hardware Manual (697 pages)
8-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 4.21 MB
Table of Contents
Table of Contents
31
Section 1 Overview
43
Overview
43
Internal Block Diagram
49
Pin Arrangement and Functions
51
Pin Arrangement
51
Pin Functions
61
Section 2 CPU
67
Overview
67
Features
67
Address Space
68
Register Configuration
68
Register Descriptions
69
General Registers
69
Control Registers
69
Initial Register Values
71
Data Formats
71
Data Formats in General Registers
72
Memory Data Formats
73
Addressing Modes
74
Effective Address Calculation
76
Instruction Set
80
Data Transfer Instructions
82
Arithmetic Operations
84
Logic Operations
85
Shift Operations
86
Bit Manipulations
88
Branching Instructions
92
System Control Instructions
94
Block Data Transfer Instruction
95
Basic Operational Timing
97
Access to On-Chip Memory (RAM, ROM)
97
Access to On-Chip Peripheral Modules
98
CPU States
99
Overview
99
Program Execution State
101
Program Halt State
101
Exception-Handling State
101
Memory Map
102
Application Notes
108
Notes on Data Access
108
Notes on Bit Manipulation
110
Notes on Use of the EEPMOV Instruction
116
Section 3 Exception Handling
117
Overview
117
Reset
117
Reset Sequence
117
Interrupt Immediately after Reset
118
Interrupts
119
Overview
119
Interrupt Control Registers
121
External Interrupts
132
Internal Interrupts
133
Interrupt Operations
134
Interrupt Response Time
139
Application Notes
140
Notes on Stack Area Use
140
Notes on Rewriting Port Mode Registers
141
Method for Clearing Interrupt Request Flags
143
Section 4 Clock Pulse Generators
145
Overview
145
Block Diagram
145
System Clock and Subclock
146
Register Descriptions
147
System Clock Generator
148
Subclock Generator
153
Prescalers
155
Note on Oscillators
156
Definition of Oscillation Stabilization Wait Time
157
Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
159
Note on Use of HD64F38024
160
Notes on H8/38124 Group
160
Section 5 Power-Down Modes
161
Overview
161
System Control Registers
164
Sleep Mode
168
Transition to Sleep Mode
168
Clearing Sleep Mode
169
Clock Frequency in Sleep (Medium-Speed) Mode
169
Standby Mode
170
Transition to Standby Mode
170
Clearing Standby Mode
170
Oscillator Stabilization Time after Standby Mode Is Cleared
170
Standby Mode Transition and Pin States
172
Notes on External Input Signal Changes Before/After Standby Mode
173
Watch Mode
174
Transition to Watch Mode
174
Clearing Watch Mode
175
Oscillator Stabilizationtime after Watch Mode Is Cleared
175
Notes on External Input Signal Changes Before/After Watch Mode
175
Subsleep Mode
176
Transition to Subsleep Mode
176
Clearing Subsleep Mode
176
Subactive Mode
177
Transition to Subactive Mode
177
Clearing Subactive Mode
177
Operating Frequency in Subactive Mode
177
Active (Medium-Speed) Mode
178
Transition to Active (Medium-Speed) Mode
178
Clearing Active (Medium-Speed) Mode
178
Operating Frequency in Active (Medium-Speed) Mode
178
Direct Transfer
179
Overview of Direct Transfer
179
Direct Transition Times
180
Notes on External Input Signal Changes Before/After Direct Transition
182
Module Standby Mode
183
Setting Module Standby Mode
183
Clearing Module Standby Mode
183
Section 6 ROM
185
Overview
185
Block Diagram
185
H8/38024 PROM Mode
186
Setting to PROM Mode
186
Socket Adapter Pin Arrangement and Memory Map
186
H8/38024 Programming
189
Writing and Verifying
189
Programming Precautions
194
Reliability of Programmed Data
195
Flash Memory Overview
196
Features
196
Block Diagram
197
Block Configuration
198
Register Configuration
200
Descriptions of Registers of the Flash Memory
200
Flash Memory Control Register 1 (FLMCR1)
200
Flash Memory Control Register 2 (FLMCR2)
203
Erase Block Register (EBR)
204
Flash Memory Power Control Register (FLPWCR)
204
Flash Memory Enable Register (FENR)
205
On-Board Programming Modes
206
Boot Mode
206
Programming/Erasing in User Program Mode
209
Notes on On-Board Programming
210
Flash Memory Programming/Erasing
210
Program/Program-Verify
210
Erase/Erase-Verify
214
Interrupt Handling When Programming/Erasing Flash Memory
214
Program/Erase Protection
216
Hardware Protection
216
Software Protection
216
Error Protection
217
Programmer Mode
217
Socket Adapter
217
Programmer Mode Commands
218
Memory Read Mode
221
Auto-Program Mode
224
Auto-Erase Mode
226
Status Read Mode
227
Status Polling
229
Programmer Mode Transition Time
230
Notes on Memory Programming
230
Power-Down States for Flash Memory
231
Section 7 RAM
233
Overview
233
Block Diagram
233
Section 8 I/O Ports
235
Overview
235
Port 1
237
Overview
237
Register Configuration and Description
237
Pin Functions
242
Pin States
243
MOS Input Pull-Up
243
Port 3
244
Overview
244
Register Configuration and Description
244
Pin Functions
249
Pin States
250
MOS Input Pull-Up
250
Port 4
251
Overview
251
Register Configuration and Description
251
Pin Functions
253
Pin States
254
Port 5
255
Overview
255
Register Configuration and Description
255
Pin Functions
258
Pin States
259
MOS Input Pull-Up
259
Port 6
260
Overview
260
Register Configuration and Description
260
Pin Functions
262
Pin States
263
MOS Input Pull-Up
263
Port 7
264
Overview
264
Register Configuration and Description
264
Pin Functions
266
Pin States
266
Port 8
267
Overview
267
Register Configuration and Description
267
Pin Functions
269
Pin States
269
Port 9
270
Overview
270
Register Configuration and Description
271
Pin Functions
274
Pin States
274
Port a
275
Overview
275
Register Configuration and Description
275
Pin Functions
277
Pin States
278
Port B
279
Overview
279
Register Configuration and Description
279
Pin Functions
281
Input/Output Data Inversion Function
282
Overview
282
Register Configuration and Descriptions
283
Note on Modification of Serial Port Control Register
284
Application Note
285
The Management of the Un-Use Terminal
285
Section 9 Timers
287
Overview
287
Timer a
288
Overview
288
Register Descriptions
290
Timer Operation
293
Timer a Operation States
294
Application Note
294
Timer C
295
Overview
295
Register Descriptions
297
Timer Operation
300
Timer C Operation States
302
Timer F
303
Overview
303
Register Descriptions
306
CPU Interface
313
Operation
316
Application Notes
319
Timer G
323
Overview
323
Register Descriptions
325
Noise Canceler
330
Operation
332
Application Notes
337
Timer G Application Example
341
Watchdog Timer
342
Overview
342
Register Descriptions
345
Timer Operation
351
Watchdog Timer Operation States
352
Asynchronous Event Counter (AEC)
353
Overview
353
Register Configurations
356
Operation
365
Asynchronous Event Counter Operation Modes
370
Application Notes
370
Section 10 Serial Communication Interface
373
Overview
373
Features
373
Block Diagram
375
Pin Configuration
376
Register Configuration
376
Register Descriptions
377
Receive Shift Register (RSR)
377
Receive Data Register (RDR)
377
Transmit Shift Register (TSR)
378
Transmit Data Register (TDR)
378
Serial Mode Register (SMR)
379
Serial Control Register 3 (SCR3)
382
Serial Status Register (SSR)
386
Bit Rate Register (BRR)
390
Clock Stop Register 1 (CKSTPR1)
396
Serial Port Control Register (SPCR)
396
Operation
398
Overview
398
Operation in Asynchronous Mode
402
Operation in Synchronous Mode
411
Multiprocessor Communication Function
418
Interrupts
425
Application Notes
426
Section 11 10-Bit PWM
431
Overview
431
Features
431
Block Diagram
432
Pin Configuration
433
Register Configuration
434
Register Descriptions
434
PWM Control Register (Pwcrm)
434
PWM Data Registers U and L (Pwdrum, Pwdrlm)
436
Clock Stop Register 2 (CKSTPR2)
437
Operation
438
PWM Operation Modes
439
Section 12 A/D Converter
441
Overview
441
Features
441
Block Diagram
442
Pin Configuration
443
Register Configuration
443
Register Descriptions
444
A/D Result Registers (ADRRH, ADRRL)
444
A/D Mode Register (AMR)
444
A/D Start Register (ADSR)
446
Clock Stop Register 1 (CKSTPR1)
447
Operation
448
A/D Conversion Operation
448
Start of A/D Conversion by External Trigger Input
448
A/D Converter Operation Modes
449
Interrupts
449
Typical Use
449
A/D Conversion Accuracy Definitions
453
Application Notes
455
Permissible Signal Source Impedance
455
Influences on Absolute Precision
455
Additional Usage Notes
456
Section 13 LCD Controller/Driver
457
Overview
457
Features
457
Block Diagram
458
Pin Configuration
460
Register Configuration
460
Register Descriptions
461
LCD Port Control Register (LPCR)
461
LCD Control Register (LCR)
463
LCD Control Register 2 (LCR2)
465
Clock Stop Register 2 (CKSTPR2)
467
Operation
468
Settings up to LCD Display
468
Relationship between LCD RAM and Display
470
Operation in Power-Down Modes
475
Boosting the LCD Drive Power Supply
476
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
477
Overview
477
Features
477
Block Diagram
478
Pin Description
479
Register Descriptions
479
Individual Register Descriptions
479
Low-Voltage Detection Control Register (LVDCR)
479
Low-Voltage Detection Status Register (LVDSR)
482
Low-Voltage Detection Counter (LVDCNT)
484
Clock Stop Register 2 (CKSTPR2)
484
Operation
485
Power-On Reset Circuit
485
Low-Voltage Detection Circuit
486
Section 15 Power Supply Circuit (H8/38124 Group Only)
493
When Using Internal Power Supply Step-Down Circuit
493
When Not Using Internal Power Supply Step-Down Circuit
494
Section 16 Electrical Characteristics
495
H8/38024 Group ZTAT Version and Mask ROM Version Absolute Maximum Ratings
495
H8/38024 Group ZTAT Version and Mask ROM Version Electrical Characteristics
496
Power Supply Voltage and Operating Range
496
DC Characteristics
499
AC Characteristics
505
A/D Converter Characteristics
508
LCD Characteristics
510
H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Absolute Maximum Ratings
511
H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Electrical Characteristics
512
Power Supply Voltage and Operating Range
512
DC Characteristics
515
AC Characteristics
522
A/D Converter Characteristics
525
LCD Characteristics
526
Flash Memory Characteristics
527
H8/38024S Group Mask ROM Version Absolute Maximum Ratings
529
H8/38024S Group Mask ROM Version Electrical Characteristics
530
Power Supply Voltage and Operating Range
530
DC Characteristics
533
AC Characteristics
541
A/D Converter Characteristics
545
LCD Characteristics
546
Absolute Maximum Ratings of H8/38124 Group F-ZTAT Version and Mask ROM Version
547
Electrical Characteristics of H8/38124 Group F-ZTAT Version and Mask ROM Version
548
Power Supply Voltage and Operating Ranges
548
DC Characteristics
552
AC Characteristics
561
A/D Converter Characteristics
563
LCD Characteristics
564
Flash Memory Characteristics
565
Power Supply Voltage Detection Circuit Characteristics
567
Power-On Reset Circuit Characteristics
570
Watchdog Timer Characteristics
571
Operation Timing
571
Output Load Circuit
574
Resonator Equivalent Circuit
574
Usage Note
575
Appendix A CPU Instruction Set
577
Instructions
577
Operation Code Map
585
Number of Execution States
587
Appendix B Internal I/O Registers
592
Addresses
592
Functions
597
B.2 Functions
597
Appendix C I/O Port Block Diagrams
658
Block Diagrams of Port 1
658
Block Diagrams of Port 3
661
Block Diagrams of Port 4
666
Block Diagram of Port 5
670
Block Diagram of Port 6
671
Block Diagram of Port 7
672
Block Diagram of Port 8
673
Block Diagrams of Port 9
674
Block Diagram of Port a
676
Block Diagrams of Port B
677
Appendix D Port States in the Different Processing States
680
Appendix E List of Product Codes
681
Appendix F Package Dimensions
685
Appendix G Specifications of Chip Form
689
Advertisement
Renesas H8/38124 Series Hardware Manual (661 pages)
8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series
Brand:
Renesas
| Category:
Computer Hardware
| Size: 3.78 MB
Table of Contents
Specifications
6
Table of Contents
19
Section 1 Overview
31
Overview
31
Internal Block Diagram
37
Pin Arrangement and Functions
39
Pin Arrangement
39
Pin Functions
49
Section 2 CPU
55
Overview
55
Features
55
Address Space
56
Register Configuration
56
Register Descriptions
57
General Registers
57
Control Registers
57
Initial Register Values
59
Data Formats
59
Data Formats in General Registers
60
Memory Data Formats
61
Addressing Modes
62
Effective Address Calculation
64
Instruction Set
68
Data Transfer Instructions
70
Arithmetic Operations
72
Logic Operations
73
Shift Operations
73
Bit Manipulations
75
Branching Instructions
79
System Control Instructions
81
Block Data Transfer Instruction
82
Basic Operational Timing
84
Access to On-Chip Memory (RAM, ROM)
84
Access to On-Chip Peripheral Modules
85
CPU States
87
Overview
87
Program Execution State
88
Program Halt State
88
Exception-Handling State
88
Memory Map
89
Application Notes
94
Notes on Data Access
94
Notes on Bit Manipulation
96
Notes on Use of the EEPMOV Instruction
102
Section 3 Exception Handling
103
Overview
103
Reset
103
Reset Sequence
103
Interrupt Immediately after Reset
104
Interrupts
105
Overview
105
Interrupt Control Registers
107
External Interrupts
117
Internal Interrupts
118
Interrupt Operations
119
Interrupt Response Time
124
Application Notes
125
Notes on Stack Area Use
125
Notes on Rewriting Port Mode Registers
126
Method for Clearing Interrupt Request Flags
128
Section 4 Clock Pulse Generators
131
Overview
131
Block Diagram
131
System Clock and Subclock
132
Register Descriptions
132
System Clock Generator
134
Subclock Generator
139
Prescalers
141
Note on Oscillators
142
Definition of Oscillation Stabilization Wait Time
143
Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
145
Note on Use of HD64F38024
146
Notes on H8/38124 Group
146
Section 5 Power-Down Modes
147
Overview
147
System Control Registers
150
Sleep Mode
154
Transition to Sleep Mode
154
Clearing Sleep Mode
155
Clock Frequency in Sleep (Medium-Speed) Mode
155
Standby Mode
156
Transition to Standby Mode
156
Clearing Standby Mode
156
Oscillator Stabilization Time after Standby Mode Is Cleared
157
Standby Mode Transition and Pin States
158
Notes on External Input Signal Changes Before/After Standby Mode
159
Watch Mode
161
Transition to Watch Mode
161
Clearing Watch Mode
161
Oscillator Stabilizationtime after Watch Mode Is Cleared
161
Notes on External Input Signal Changes Before/After Watch Mode
161
Subsleep Mode
162
Transition to Subsleep Mode
162
Clearing Subsleep Mode
162
Subactive Mode
163
Transition to Subactive Mode
163
Clearing Subactive Mode
163
Operating Frequency in Subactive Mode
163
Active (Medium-Speed) Mode
164
Transition to Active (Medium-Speed) Mode
164
Clearing Active (Medium-Speed) Mode
164
Operating Frequency in Active (Medium-Speed) Mode
164
Direct Transfer
165
Overview of Direct Transfer
165
Direct Transition Times
166
Notes on External Input Signal Changes Before/After Direct Transition
168
Module Standby Mode
169
Setting Module Standby Mode
169
Clearing Module Standby Mode
169
Section 6 ROM
171
Overview
171
Block Diagram
171
H8/38024 PROM Mode
172
Setting to PROM Mode
172
Socket Adapter Pin Arrangement and Memory Map
172
H8/38024 Programming
175
Writing and Verifying
175
Programming Precautions
180
Reliability of Programmed Data
181
Flash Memory Overview
182
Features
182
Block Diagram
183
Block Configuration
184
Register Configuration
185
Descriptions of Registers of the Flash Memory
186
Flash Memory Control Register 1 (FLMCR1)
186
Flash Memory Control Register 2 (FLMCR2)
188
Erase Block Register (EBR)
189
Flash Memory Power Control Register (FLPWCR)
189
Flash Memory Enable Register (FENR)
190
On-Board Programming Modes
191
Boot Mode
192
Programming/Erasing in User Program Mode
194
Notes on On-Board Programming
195
Flash Memory Programming/Erasing
195
Program/Program-Verify
195
Erase/Erase-Verify
199
Interrupt Handling When Programming/Erasing Flash Memory
199
Program/Erase Protection
201
Hardware Protection
201
Software Protection
201
Error Protection
201
Programmer Mode
202
Socket Adapter
202
Programmer Mode Commands
202
Memory Read Mode
205
Auto-Program Mode
208
Auto-Erase Mode
210
Status Read Mode
211
Status Polling
213
Programmer Mode Transition Time
213
Notes on Memory Programming
214
Power-Down States for Flash Memory
214
Section 7 RAM
215
Overview
215
Block Diagram
215
Section 8 I/O Ports
217
Overview
217
Port 1
219
Overview
219
Register Configuration and Description
219
Pin Functions
224
Pin States
225
MOS Input Pull-Up
225
Port 3
226
Overview
226
Register Configuration and Description
226
Pin Functions
231
Pin States
232
MOS Input Pull-Up
232
Port 4
233
Overview
233
Register Configuration and Description
233
Pin Functions
235
Pin States
236
Port 5
237
Overview
237
Register Configuration and Description
237
Pin Functions
240
Pin States
241
MOS Input Pull-Up
241
Port 6
242
Overview
242
Register Configuration and Description
242
Pin Functions
244
Pin States
245
MOS Input Pull-Up
245
Port 7
246
Overview
246
Register Configuration and Description
246
Pin Functions
248
Pin States
248
Port 8
249
Overview
249
Register Configuration and Description
249
Pin Functions
251
Pin States
251
Port 9
252
Overview
252
Register Configuration and Description
252
Pin Functions
255
Pin States
255
Overview
256
Register Configuration and Description
256
Pin Functions
258
Pin States
259
Overview
260
Register Configuration and Description
260
Pin Functions
262
Input/Output Data Inversion Function
263
Overview
263
Register Configuration and Descriptions
264
Note on Modification of Serial Port Control Register
265
Application Note
266
The Management of the Un-Use Terminal
266
Section 9 Timers
267
Overview
267
Timer a
268
Overview
268
Register Descriptions
270
Timer Operation
273
Timer a Operation States
273
Application Note
274
Timer C
274
Overview
274
Register Descriptions
276
Timer Operation
279
Timer C Operation States
281
Timer F
282
Overview
282
Register Descriptions
285
CPU Interface
292
Operation
295
Application Notes
298
Timer G
301
Overview
301
Register Descriptions
303
Noise Canceler
308
Operation
310
Application Notes
314
Timer G Application Example
319
Watchdog Timer
320
Overview
320
Register Descriptions
323
Timer Operation
329
Watchdog Timer Operation States
330
Asynchronous Event Counter (AEC)
331
Overview
331
Register Configurations
334
Operation
343
Asynchronous Event Counter Operation Modes
347
Application Notes
348
Section 10 Serial Communication Interface
349
Overview
349
Features
349
Block Diagram
351
Pin Configuration
352
Register Configuration
352
Register Descriptions
353
Receive Shift Register (RSR)
353
Receive Data Register (RDR)
353
Transmit Shift Register (TSR)
354
Transmit Data Register (TDR)
354
Serial Mode Register (SMR)
355
Serial Control Register 3 (SCR3)
358
Serial Status Register (SSR)
362
Bit Rate Register (BRR)
366
Clock Stop Register 1 (CKSTPR1)
372
Serial Port Control Register (SPCR)
372
Operation
374
Overview
374
Operation in Asynchronous Mode
378
Operation in Synchronous Mode
387
Data Transfer Operations
389
Synchronous Mode
393
Multiprocessor Communication Function
394
Interrupts
401
Application Notes
402
Section 11 10-Bit PWM
407
Overview
407
Features
407
Block Diagram
408
Pin Configuration
409
Register Configuration
410
Register Descriptions
410
PWM Control Register (Pwcrm)
410
PWM Data Registers U and L (Pwdrum, Pwdrlm)
412
Clock Stop Register 2 (CKSTPR2)
413
Operation
414
PWM Operation Modes
415
Section 12 A/D Converter
417
Overview
417
Features
417
Block Diagram
418
Pin Configuration
419
Register Configuration
419
Register Descriptions
420
A/D Result Registers (ADRRH, ADRRL)
420
A/D Mode Register (AMR)
420
A/D Start Register (ADSR)
422
Clock Stop Register 1 (CKSTPR1)
423
Operation
424
A/D Conversion Operation
424
Start of A/D Conversion by External Trigger Input
424
A/D Converter Operation Modes
425
Interrupts
425
Typical Use
425
A/D Conversion Accuracy Definitions
428
Application Notes
430
Permissible Signal Source Impedance
430
Influences on Absolute Precision
430
Section 13 LCD Controller/Driver
433
Overview
433
Features
433
Block Diagram
434
Pin Configuration
436
Register Configuration
436
Register Descriptions
437
LCD Port Control Register (LPCR)
437
LCD Control Register (LCR)
439
LCD Control Register 2 (LCR2)
441
Clock Stop Register 2 (CKSTPR2)
443
Operation
444
Settings up to LCD Display
444
Relationship between LCD RAM and Display
446
Operation in Power-Down Modes
451
Boosting the LCD Drive Power Supply
452
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
453
Overview
453
Features
453
Block Diagram
454
Pin Description
455
Register Descriptions
455
Individual Register Descriptions
455
Low-Voltage Detection Control Register (LVDCR)
455
Low-Voltage Detection Status Register (LVDSR)
458
Low-Voltage Detection Counter (LVDCNT)
460
Clock Stop Register 2 (CKSTPR2)
460
Operation
461
Power-On Reset Circuit
461
Low-Voltage Detection Circuit
462
Section 15 Power Supply Circuit (H8/38124 Group Only)
469
When Using Internal Power Supply Step-Down Circuit
469
When Not Using Internal Power Supply Step-Down Circuit
470
Section 16 Electrical Characteristics
471
H8/38024 ZTAT Version and Mask ROM Version Absolute Maximum Ratings
471
H8/38024 ZTAT Version and Mask ROM Version Electrical Characteristics
472
Power Supply Voltage and Operating Range
472
DC Characteristics
474
AC Characteristics
480
A/D Converter Characteristics
483
LCD Characteristics
484
H8/38024 F-ZTAT Version and H8/38024R F-ZTAT Version Absolute Maximum Ratings
485
H8/38024 F-ZTAT Version and H8/38024R F-ZTAT Version Electrical Characteristics
486
Power Supply Voltage and Operating Range
486
DC Characteristics
488
AC Characteristics
494
A/D Converter Characteristics
497
LCD Characteristics
498
Flash Memory Characteristics
499
H8/38024S Group Mask ROM Version Absolute Maximum Ratings
501
H8/38024S Group Mask ROM Version Electrical Characteristics
502
Power Supply Voltage and Operating Range
502
DC Characteristics
504
AC Characteristics
511
A/D Converter Characteristics
514
LCD Characteristics
515
Absolute Maximum Ratings of H8/38124 Group
516
Electrical Characteristics of H8/38124 Group
517
Power Supply Voltage and Operating Ranges
517
DC Characteristics
521
AC Characteristics
530
A/D Converter Characteristics
532
LCD Characteristics
533
Flash Memory Characteristics
534
Power Supply Voltage Detection Circuit Characteristics
536
Power-On Reset Circuit Characteristics
539
Watchdog Timer Characteristics
540
Operation Timing
540
Output Load Circuit
543
Resonator Equivalent Circuit
543
Usage Note
544
Appendix A CPU Instruction Set
545
Instructions
545
Operation Code Map
553
Number of Execution States
555
Appendix B Internal I/O Registers
560
Addresses
560
Functions
565
B.2 Functions
565
Appendix C I/O Port Block Diagrams
626
Block Diagrams of Port 1
626
Block Diagrams of Port 3
629
Block Diagrams of Port 4
634
Block Diagram of Port 5
638
Block Diagram of Port 6
639
Block Diagram of Port 7
640
Block Diagram of Port 8
641
Block Diagrams of Port 9
642
Block Diagram of Port a
643
Block Diagram of Port B
644
Appendix D Port States in the Different Processing States
645
Appendix E List of Product Codes
646
Appendix F Package Dimensions
649
Appendix G Specifications of Chip Form
653
Appendix H Form of Bonding Pads
655
Appendix I Specifications of Chip Tray
656
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