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Table A.1 lists the H8/300L CPU instruction set.
Table A.1
Instruction Set
Mnemonic
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @Rs, Rd
MOV.B @(d:16, Rs), Rd
MOV.B @Rs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @−Rd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) → Rd16
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
MOV.W Rs, @(d:16, Rd) W Rs16 → @(d:16, Rd16)
MOV.W Rs, @−Rd
MOV.W Rs, @aa:16
POP Rd
PUSH Rs
Rev. 6.00, 08/04, page 516 of 628
Operation
B #xx:8 → Rd8
B Rs8 → Rd8
B @Rs16 → Rd8
B @(d:16, Rs16)→ Rd8
B @Rs16 → Rd8
Rs16+1 → Rs16
B @aa:8 → Rd8
B @aa:16 → Rd8
B Rs8 → @Rd16
B Rs8 → @(d:16, Rd16)
B Rd16−1 → Rd16
Rs8 → @Rd16
B Rs8 → @aa:8
B Rs8 → @aa:16
W #xx:16 → Rd
W Rs16 → Rd16
W @Rs16 → Rd16
W @Rs16 → Rd16
Rs16+2 → Rs16
W @aa:16 → Rd16
W Rs16 → @Rd16
W Rd16−2 → Rd16
Rs16 → @Rd16
W Rs16 → @aa:16
W @SP → Rd16
SP+2 → SP
W SP−2 → SP
Rs16 → @SP
Addressing Mode/
Instruction Length (bytes)
2
2
2
4
2
2
4
2
4
2
2
4
4
2
2
4
2
4
2
4
2
4
2
2
Condition Code
I H N Z V C
0 2
0 2
0 4
0 6
0 6
0 4
0 6
0 4
0 6
0 6
0 4
0 6
0 4
0 2
0 4
0 6
0 6
0 6
0 4
0 6
0 6
0 6
0 6
0 6
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