Renesas H8/38024 Hardware Manual page 585

TCSRW—Timer Control/Status Register W
Bit 7
B6WI
Initial value 1
Read/Write R
Bit 6 Write Inhibit
0 Bit 6 is write-enabled
1 Bit 6 is write-disabled
Notes: 1. Write is permitted only under certain conditions.
2. 1 on the H8/38124 Group.
6 5
TCWE B4WI
0 1
R/(W) *
1
R
Timer Control/Status Register W Write Enable
0
1
Bit 4 Write Inhibit
0 Bit 4 is write-enabled
1 Bit 4 is write-disabled
Timer Counter W Write Enable
0 8-bit data cannot be written to TCW
1 8-bit data can be written to TCW
H'B2
4 3
TCSRWE B2WI
0 1
R/(W) *
1
R
Watchdog Timer Reset
0
1
Bit 0 Write Inhibit
0 Bit 0 is write-enabled
1 Bit 0 is write-disabled
Watchdog Timer On
0 Watchdog timer operation is disabled
Clearing conditions:
Reset *
2
, or 0 is written in both B2WI and WDON
while TCSRWE = 1
1 Watchdog timer operation is enabled
Setting condition:
0 is written in B2WI and 1 is written in WDON
while TCSRWE = 1
Bit 2 Write Inhibit
0 Bit 2 is write-enabled
1 Bit 2 is write-disabled
Data cannot be written to bits 2 and 0
Data can be written to bits 2 and 0
Rev. 6.00, 08/04, page 555 of 628
Watchdog Timer
2 1
WDON BOWI WRST
0 *
2
1
R/(W) * R/(W) *
1
R
Clearing conditions:
Reset by RES pin
When TCSRWE = 1, and 0 is written
in both B0WI and WRST
Setting condition:
When TCW overflows and an internal
reset signal is generated
0
0
1