Renesas H8/38024 Hardware Manual page 111

8-bit single-chip microcomputer h8 family/h8/300l super low power series
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Bit 4—Timer G Interrupt Enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG
Description
0
Disables timer G interrupt requests
1
Enables timer G interrupt requests
Bit 3—Timer FH Interrupt Enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
Description
0
Disables timer FH interrupt requests
1
Enables timer FH interrupt requests
Bit 2—Timer FL Interrupt Enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
Description
0
Disables timer FL interrupt requests
1
Enables timer FL interrupt requests
Bit 1—Timer C Interrupt Enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC
Description
0
Disables timer C interrupt requests
1
Enables timer C interrupt requests
(initial value)
(initial value)
(initial value)
(initial value)
Rev. 6.00, 08/04, page 81 of 628

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