Renesas H8/38024 Hardware Manual page 495

Item Symbol
External clock low t
CPL
width
External clock rise t
CPr
time
External clock fall t
CPf
time
Pin RES low width
t
REL
Input pin high width t
IH
Input pin low width t
IL
UD pin minimum t
UDH
transition width t
UDL
Notes: 1. Selected with SA1 and SA0 of system control register 2 (SYSCR2).
2. The figure in parentheses applies when an external clock is used.
3. Applies to the HD64F38024R.
4. Applies to the HD64F38024.
Applicable
Pins
Min Typ
OSC 40 —
1
X — 15.26
1
or
13.02
OSC — —
1
X — —
1
OSC — —
1
X — —
1
RES
10 —
IRQ , IRQ
, 2 —
0 1
IRQ , IRQ
,
3 4
IRQAEC,
WKP
to
0
WKP
,
7
TMIC, TMIF,
TMIG, ADTRG
AEVL, AEVH 0.5 —
IRQ , IRQ
, 2 —
0 1
IRQ , IRQ
,
3 4
IRQAEC,
WKP
to
0
WKP
,
7
TMIC, TMIF,
TMIG, ADTRG
AEVL, AEVH 0.5 —
UD 4 —
Values
Max Unit Test Condition
— ns
— µs
10 ns
55.0 ns
10 ns
55.0 ns
— t
cyc
— t
cyc
t
subcyc
— t
osc
— t
cyc
t
subcyc
— t
osc
— t
cyc
t
subcyc
Rev. 6.00, 08/04, page 465 of 628
Reference
Figure
Figure 16.1
Figure 16.1
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.3
Figure 16.6