Clock Stop Register 2 (Ckstpr2) - Renesas H8/38024 Hardware Manual

13.2.4

Clock Stop Register 2 (CKSTPR2)

Bit
LVDCKSTP *
Initial value
Read/Write R/W
Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the LCD controller/driver is described here. For details of the
other bits, see the sections on the relevant modules.
Bit 0—LCD Controller/Driver Module Standby Mode Control (LDCKSTP)
Bit 0 controls setting and clearing of module standby mode for the LCD controller/driver.
Bit 0
LDCKSTP Description
0 LCD controller/driver is set to module standby mode
1 LCD controller/driver module standby mode is cleared
7 6 5
 
1 1 1
 
4 3
PW2CKSTP
AECKSTP WDCKSTP
1 1
R/W R/W
Rev. 6.00, 08/04, page 413 of 628
2 1
PW1CKSTP LDCKSTP
1 1
R/W R/W R/W
(initial value)
0
1