Renesas H8/38024 Hardware Manual page 376

Table 10.9 SMR and SCR3 Settings and Clock Source Selection
SMR SCR3
Bit 7 Bit 1 Bit 0
COM CKE1 CKE0 Mode
0 0 0
1
1 0
1 0 0
1 0
0 1 1
1 0 1
1 1 1
Interrupts and Continuous Transmission/Reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10.10.
Table 10.10 Transmit/Receive Interrupts
Interrupt Flags Interrupt Request Conditions
RXI RDRF When serial reception is performed
RIE normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10.2(a).)
TXI TDRE When TSR is found to be empty (on
TIE completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10.2(b).)
TEI TEND When the last bit of the character in
TEIE TSR is transmitted, if bit TDRE is set to
1, bit TEND is set to 1. If bit TEIE is set
to 1 at this time, TEI is enabled and an
interrupt is requested. (See figure
10.2(c).)
Rev. 6.00, 08/04, page 346 of 628
Clock Source SCK
Asynchronous Internal
mode
External
Synchronous Internal
mode
External
Reserved (Do not specify these combinations)
Transmit/Receive Clock
Pin Function
32
I/O port (SCK pin not used)
32
Outputs clock with same frequency as bit rate
Inputs clock with frequency 16 times bit rate
Outputs serial clock
Inputs serial clock
Notes
The RXI interrupt routine reads the
receive data transferred to RDR and
clears bit RDRF to 0. Continuous
reception can be performed by
repeating the above operations until
reception of the next RSR data is
completed.
The TXI interrupt routine writes the
next transmit data to TDR and clears
bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations until
the data transferred to TSR has
been transmitted.
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is sent.