Renesas H8/38024 Hardware Manual page 297

8-bit single-chip microcomputer h8 family/h8/300l super low power series
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TCF Clear Timing
TCF can be cleared by a compare match with OCRF.
Timer Overflow Flag (OVF) Set Timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
Compare Match Flag Set Timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
Timer F Operation Modes
Timer F operation modes are shown in table 9.9.
Table 9.9
Timer F Operation Modes
Operation Mode
Reset
TCF
Reset
OCRF
Reset
TCRF
Reset
TCSRF
Reset
Note: * When φ
/4 is selected as the TCF internal clock in active mode or sleep mode, since the
w
system clock and internal clock are mutually asynchronous, synchronization is maintained
by a synchronization circuit. This results in a maximum count cycle error of 1/φ (s). When
the counter is operated in subactive mode, watch mode, or subsleep mode, φ
selected as the internal clock. The counter will not operate if any other internal clock is
selected.
Active
Sleep
Watch
Functions Functions Functions/
Halted *
Functions Held
Held
Functions Held
Held
Functions Held
Held
Sub-
Sub-
active
sleep
Functions/
Functions/
Halted *
Halted *
Functions
Held
Functions
Held
Functions
Held
Rev. 6.00, 08/04, page 267 of 628
Module
Standby
Standby
Halted
Halted
Held
Held
Held
Held
Held
Held
/4 must be
w

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