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Pin Configuration
Table 9.10 shows the timer G pin configuration.
Table 9.10 Pin Configuration
Name
Input capture input
Register Configuration
Table 9.11 shows the register configuration of timer G.
Table 9.11 Timer G Registers
Name
Timer control register G
Timer counter G
Input capture register GF
Input capture register GR
Clock stop register 1
9.5.2
Register Descriptions
Timer Counter G (TCG)
Bit:
7
TCG7
Initial value:
0
Read/Write:
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer * . In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG in IRR2 is set to 1, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
Abbr.
I/O
TMIG
Input
Abbr.
TMG
TCG
ICRGF
ICRGR
CKSTPR1
6
5
TCG6
TCG5
0
0
Function
Input capture input pin
R/W
Initial Value
R/W
H'00
—
H'00
R
H'00
R
H'00
R/W
H'FF
4
3
TCG4
TCG3
0
0
Rev. 6.00, 08/04, page 273 of 628
Address
H'FFBC
—
H'FFBD
H'FFBE
H'FFFA
2
1
TCG2
TCG1
0
0
0
TCG0
0
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