Table of Contents
Advertisement
Interrupt Request Register 2 (IRR2)
Bit
IRRDT
Initial value
R/(W) *
Read/Write
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FL, Timer C, or asynchronous event counter
interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is
necessary to write 0 to clear each flag.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
1
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2
Bit 6—A/D Converter Interrupt Request Flag (IRRAD)
Bit 6
IRRAD
Description
0
Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
1
Setting conditions:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Bit 5—Reserved
Bit 5 is reserved: it can only be written with 0.
Rev. 6.00, 08/04, page 84 of 628
7
6
5
IRRAD
0
0
R/(W) *
W
4
3
IRRTG
IRRTFH
IRRTFL
0
0
R/(W) *
R/(W) *
R/(W) *
2
1
0
IRRTC
IRREC
0
0
0
R/(W) *
R/(W) *
(initial value)
(initial value)
Advertisement
Table of Contents
