Renesas H8/38024 Hardware Manual page 592

TMG—Timer Mode Register G
Bit 7
OVFH
Initial value 0
R/(W) *
Read/Write
Timer Overflow Flag L
Timer Overflow Flag H
0 Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1 Setting condition:
Set when TCG overflows from H'FF to H'00
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
Rev. 6.00, 08/04, page 562 of 628
6 5
OVFL OVIE
0 0
R/(W) *
R/W
Input Capture Interrupt Edge Select
0 Interrupt generated on rising edge of input capture
1 Interrupt generated on falling edge of input capture
Timer Overflow Interrupt Enable
0 TCG overflow interrupt request is disabled
1 TCG overflow interrupt request is enabled
0 Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1 Setting condition:
Set when TCG overflows from H'FF to H'00
H'BC
4 3
IIEGS CCLR1
0 0
R/W R/W
Clock Select
0 0
1 Internal clock: counting on φ/32
1 0 Internal clock: counting on φ/2
1 Internal clock: counting on φ
Counter Clear
0 0 TCG clearing is disabled
1 TCG cleared by falling edge of input capture
input signal
1 0 TCG cleared by rising edge of input capture
input signal
1 TCG cleared by both edges of input capture
input signal
input signal
input signal
2 1
CCLR0 CKS1 CKS0
0 0
R/W R/W
Internal clock: counting on φ/64
Timer G
0
0
R/W
/4
W