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Bit 3—IRQ
Edge Select (IEG3)
3
Bit 3 selects the input sensing of the IRQ
Bit 3
IEG3
Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Bit 2—Reserved
Bit 2 is reserved: it can only be written with 0.
Bit 1—IRQ
Edge Select (IEG1)
1
Bit 1 selects the input sensing of the IRQ
Bit 1
IEG1
Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Bit 0—IRQ
Edge Select (IEG0)
0
Bit 0 selects the input sensing of pin IRQ
Bit 0
IEG0
Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Interrupt Enable Register 1 (IENR1)
Bit
IENTA
Initial value
Read/Write
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Rev. 6.00, 08/04, page 78 of 628
3
and TMIF pin input is detected
3
and TMIF pin input is detected
3
1
and TMIC pin input is detected
1
and TMIC pin input is detected
1
.
0
pin input is detected
0
pin input is detected
0
7
6
5
IENWP
0
0
W
R/W
pin and TMIF pin.
pin and TMIC pin.
4
3
IEN4
IEN3
0
0
R/W
R/W
(initial value)
(initial value)
(initial value)
2
1
IENEC2
IEN1
0
0
R/W
R/W
0
IEN0
0
R/W
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