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The oscillation stabilization time in the case of these state transitions is the same as the oscillation
stabilization time at power-on (the time from the point at which the power supply voltage reaches
the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time t rc "
in the AC characteristics.
Meanwhile, once the system clock has halted, a wait time of at least 8 states is necessary in order
for the CPU and peripheral functions to operate normally.
Thus, the time required from interrupt generation until operation of the CPU and peripheral
functions is the sum of the above described oscillation stabilization time and wait time. This total
time is called the oscillation stabilization wait time, and is expressed by equation (1) below.
Oscillation stabilization wait time = oscillation stabilization time + wait time
Notes: 1. H8/38024 Group
2. H8/38124 Group
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator, careful evaluation must be carried out on the installation circuit before deciding on the
oscillation stabilization wait time. In particular, since the oscillation stabilization time is affected
by installation circuit constants, stray capacitance, and so forth, suitable constants should be
determined in consultation with the oscillator element manufacturer.
4.5.2
Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator
Element)
When a microcomputer operates, the internal power supply potential fluctuates slightly in
synchronization with the system clock. Depending on the individual crystal oscillator element
characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after
the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by
fluctuations in the power supply potential. In this state, the oscillation waveform may be
disrupted, leading to an unstable system clock and erroneous operation of the microcomputer.
If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to
STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer wait time.
For example, if erroneous operation occurs with a wait time setting of 16 states, check the
operation with a wait time setting of 1,024 * states or more.
If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES
pin low for a longer period.
+ (8 to 16,384 states) *
= t
rc
(up to 131,072 states) *
1
................. (1)
2
Rev. 6.00, 08/04, page 115 of 628
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