Renesas H8/38024 Hardware Manual page 38

x
1
x
2
OSC
1
OSC
2
P1 /TMIG
3
P1 /IRQ /ADTRG
4 4
P1 /IRQ /TMIF
7 3
P3 /UD
0
P3 /TMOFL
1
P3 /TMOFH
2
P3
3
P3
4
P3
5
P3 /AEVH
6
P3 /AEVL
7
P4 /SCK
0 32
P4 /RXD
1 32
P4 /TXD
2 32
P4 /IRQ
3 0
P5 /WKP /SEG
0 0 1
P5 /WKP /SEG
1 1 2
P5 /WKP /SEG
2 2 3
P5 /WKP /SEG
3 3 4
P5 /WKP /SEG
4 4 5
P5 /WKP /SEG
5 5 6
P5 /WKP /SEG
6 6 7
P5 /WKP /SEG
7 7 8
P6 /SEG
0 9
P6 /SEG
1 10
P6 /SEG
2 11
P6 /SEG
3 12
P6 /SEG
4 13
P6 /SEG
5 14
P6 /SEG
6 15
P6 /SEG
7 16
AV
CC
Note: If the on-chip emulator is used, pins 95,
33, 34, and 35 are reserved for the
emulator and not available to the user.
Rev. 6.00, 08/04, page 8 of 628
Sub clock
OSC
System clock
OSC
ROM
(8 Kbytes to 32 Kbytes)
Power-on reset and
low-voltage detect circuits
Timer A
Timer C
Timer G
Asynchronous
counter
(16 bits)
A/D
(10 bits)
Figure 1.1(2) Block Diagram (H8/38124 Group)
H8/300L
CPU
RAM
(512 bytes to 1 Kbyte)
10-bit PWM1
10-bit PWM2
Timer F
Serial
communication
interface
(SCI3)
WDT
LCD
controller
Large-current (15 mA/pin)
CV
CC
V
SS
V = AV
SS SS
V
CC
RES
TEST
PA /COM
3 4
PA /COM
2 3
PA /COM
1 2
PA /COM
0 1
IRQAEC
P9
5
P9
4
P9 /V
3 ref
P9
2
P9 /PWM
1 2
P9 /PWM
0 1
P8 /SEG
7 32
P8 /SEG
6 31
P8 /SEG
5 30
P8 /SEG
4 29
P8 /SEG
3 28
P8 /SEG
2 27
P8 /SEG
1 26
P8 /SEG
0 25
P7 /SEG
7 24
P7 /SEG
6 23
P7 /SEG
5 22
P7 /SEG
4 21
P7 /SEG
3 20
P7 /SEG
2 19
P7 /SEG
1 18
P7 /SEG
0 17
V
1
V
2
V
3
PB /AN
7 7
PB /AN
6 6
PB /AN
5 5
PB /AN
4 4
PB /AN /IRQ /TMIC
3 3 1
PB /AN
2 2
PB /AN /extU
1 1
PB /AN /extD
0 0