Renesas H8/38024 Hardware Manual page 288

Bit 3—Toggle Output Level L (TOLL)
Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is
written.
Bit 3
TOLL Description
0 Low level
1 High level
Bits 2 to 0—Clock Select L (CKSL2 to CKSL0)
Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event
input.
Bit 2 Bit 1
CKSL2 CKSL1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note: * External event edge selection is set by IEG3 in the IRQ edge select register (IEGR). For
details, see IRQ Edge Select Register (IEGR) in section 3.3.2.
Note that the timer F counter may increment if the setting of IRQ3 in port mode register 1
(PMR1) is changed from 0 to 1 or from 1 to 0 while the TMIF pin is low in order to change
the TMIF pin function.
Rev. 6.00, 08/04, page 258 of 628
Bit 0
CKSL0 Description
Counting on external event (TMIF) rising/falling edge *
0
1
0
1 Use prohibited
Internal clock: counting on φ/32
0
Internal clock: counting on φ/16
1
Internal clock: counting on φ/4
0
Internal clock: counting on φw/4
1
(initial value)
(initial value)