Renesas H8/38024 Hardware Manual page 338

Bits 5 and 4—AEC Clock Select L (ACKL1, ACKL0)
Bits 5 and 4 select the clock used by ECL.
Bit 5 Bit 4
ACKL1 ACKL0
0 0
1
1 0
1
Bits 3 to 1—Event Counter PWM Clock Select (PWCK2, PWCK1, PWCK0)
Bits 3 to 1 select the event counter PWM clock.
Bit 3 Bit 2
PWCK2 PWCK1
0 0
1
1 *
Bit 0—Reserved
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
Rev. 6.00, 08/04, page 308 of 628
Description
AEVL pin input
φ/2
φ/4
φ/8
Bit 1
PWCK0 Description
φ/2
0
φ/4
1
φ/8
0
φ/16
1
φ/32
0
φ/64
1
(initial value)
(initial value)
*: Don't care