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counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by software,
and is also initialized to H'00 upon reset.
Event Counter L (ECL)
Bit
7
ECL7
Initial Value
0
Read/Write
R
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin, φ/2, φ/4, or φ/8 is used as the input
clock source. ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset.
Clock Stop Register 2 (CKSTPR2)
Bit
7
LVDCKSTP *
Initial value
1
Read/Write
R/W
Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
Bit 3—Asynchronous Event Counter Module Standby Mode Control (AECKSTP)
Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.
AECKSTP
Description
0
Asynchronous event counter is set to module standby mode
1
Asynchronous event counter module standby mode is cleared
Rev. 6.00, 08/04, page 312 of 628
6
5
ECL6
ECL5
ECL4
0
0
R
R
6
5
PW2CKSTP AECKSTP
1
1
R/W
4
3
ECL3
ECL2
0
0
R
R
4
3
WDCKSTP PW1CKSTP LDCKSTP
1
1
R/W
R/W
2
1
ECL1
ECL0
0
0
R
R
2
1
1
1
R/W
R/W
(initial value)
0
0
R
0
1
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