Renesas H8/38024 Hardware Manual page 368

Table 10.4 Relation between n and Clock
n Clock
φ
0
φw/2 * 1
/φw *
0
φ/16
2
φ/64
3
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
OSC (MHz)
0.0384 *
2
2.4576
4
10
16
Note: * When SMR is set up to CKS1 = 0, CKS0 = 1.
Rev. 6.00, 08/04, page 338 of 628
CKS1
0
2
0
1
1
Maximum Bit Rate
(bit/s)
600
31250
38400
62500
156250
250000
SMR Setting
CKS0
0
1
0
1
Setting
n N
0 0
0 0
0 0
0 0
0 0
0 0