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9.7.5
Application Notes
1. When reading the values in ECH and ECL, the correct value will not be returned if the event
counter increments during the read operation. Therefore, if the counter is being used in the 8-
bit mode, clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL. If the
counter is being used in the 16-bit mode, clear CUEL only to 0 before reading ECH or ECL.
2. Use a clock with a frequency of up to 16 MHz for input to the AEVH and AEVL pins, and
ensure that the high and low widths of the clock are at least 30 ns. The duty cycle is
immaterial.
Mode
Active (high-speed), sleep (high-speed)
Active (medium-speed), sleep (medium-speed) (φ/16)
f
= 1 MHz to 4 MHz
OSC
Watch, subactive, subsleep, standby
φw = 32.768 kHz or 38.4 kHz
3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.
Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change
the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may
occur. Also, to reset the counter, clear CRCH and CRCL to 0 simultaneously or clear CRCL
and CRCH to 0 sequentially, in that order.
4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH,
ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 t
Rev. 6.00, 08/04, page 318 of 628
will occur between clock halting and interrupt acceptance.
cyc
Maximum AEVH/AEVL Pin Input
Clock Frequency
16 MHz
2 • f
OSC
(φ/32)
f
OSC
(φ/64)
1/2 • f
OSC
(φ/128)
1/4 • f
OSC
(φw/2)
1000 kHz
(φw/4)
500 kHz
(φw/8)
250 kHz
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