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4.1.1 Block Diagram
Figure 4.2 Block
Diagram of Clock Pulse
Generators (H8/38124
Group)
4.2 System Clock
Generator
Table 4.2 Crystal
Oscillator Parameters
On-Chip Oscillator
Selection Method
(H8/38124 Group Only)
4.4 Prescalers
4.5.1 Definition of
Oscillation Stabilization
Wait Time
5.1 Overview
Table 5.1 Operating
Modes
5.5.2 Clearing
Subsleep Mode
Rev. 6.00, 08/04, page x of xxx
Page
Revisions (See Manual for Details)
102
Figure 4.2 amended
(Before) Internal reset signal → (After) Internal reset signal
(other than watchdog timer or low-voltage detect circuit reset)
105
Table 4.2
Frequency (MHz)
108
Note added
The on-chip oscillator is selected by setting the IRQAEC pin
input level during resets.*
* Other than watchdog timer or low-voltage detect circuit
reset.
111
Prescalers S (PPS)
Description amended
The output from prescaler S is shared by timer A, timer C, timer
F, timer G, SCI3, the A/D converter, the LCD controller,
watchdog timer, and the 10-bit PWM. The divider ratio can be
set separately for each on-chip peripheral function.
115
2. Wait time
Description amended, notes *1, *2 added
Oscillation stabilization wait time = oscillation stabilization time + wait time
Notes: 1. H8/38024 Group
2. H8/38124 Group
117
Table 5.1 amended
Operating Mode
Watch mode
132
• Clearing by interrupt
To synchronize is requested signal with the system clock, up to
2/φ
(s) delay may occur after the interrupt request signal
SUB
occurrence, before the interrupt exception handling start.
4
+ (8 to 16,384 states) *
= t
rc
(to 131,072 states) *
Description
The CPU halts. The time-base function of timer A, timer F,
timer G, AEC and LCD controller/driver are operable on the
subclock
4.193
1
................. (1)
2
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