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10.1.2
Block Diagram
Figure 10.1 shows a block diagram of SCI3.
External
SCK
32
clock
Clock
TXD
32
SPCR
RXD
32
[Legend]
RSR:
Receive shift register
RDR:
Receive data register
TSR:
Transmit shift register
TDR:
Transmit data register
SMR:
Serial mode register
SCR3:
Serial control register 3
SSR:
Serial status register
BRR:
Bit rate register
BRC:
Bit rate counter
SPCR:
Serial port control register
Baud rate generator
BRC
Transmit/receive
control circuit
TSR
RSR
Figure 10.1 SCI3 Block Diagram
Internal clock (φ/64, φ/16, φ
BRR
SMR
SCR3
SSR
TDR
RDR
Rev. 6.00, 08/04, page 321 of 628
/2, φ)
W
Interrupt request
(TEI, TXI, RXI, ERI)
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