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IRR1—Interrupt Request Register 1
Bit
7
IRRTA
Initial value
0
R/(W) *
Read/Write
Timer A Interrupt Request Flag
0 Clearing condition:
1 Setting condition:
Note: * Bits 7 and 4 to 0 can only be written with 0, for flag clearing.
Rev. 6.00, 08/04, page 590 of 628
6
5
1
W
IRQAEC Interrupt Request Flag
0 Clearing condition:
1 Setting condition:
When pin IRQAEC is designated for interrupt
input and the designated signal edge is input
IRQ4 and IRQ3 Interrupt Request Flags
0 Clearing condition:
When IRRIm = 1, it is cleared by writting 0
1 Setting condition:
When pin IRQm is designated for interrupt
input and the designated signal edge is input
When IRRTA = 1, it is cleared by writing 0
When the timer A counter value overflows (from H'FF to H'00)
H'F6
4
3
IRRI4
IRRI3
0
0
R/(W) *
R/(W) *
IRQ1 and IRQ0 Interrupt Request Flags
0 Clearing condition:
When IRRIn = 1, it is cleared by writing 0
1 Setting condition:
When pin IRQn is designated for interrupt
input and the designated signal edge is input
When IRREC2 = 1, it is cleared by writing 0
System Control
2
1
IRREC2
IRRI1
0
0
R/(W) *
R/(W) *
R/(W) *
(m = 4 or 3)
0
IRRI0
0
(n = 1 or 0)
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