Renesas H8/38024 Hardware Manual page 580

SCR3—Serial Control Register 3
Bit 7
TIE
Initial value 0
Read/Write R/W
Clock Enable
Bit 1
CKE1
0
0
1
1
Transmit End Interrupt Enable
0 Transmit end interrupt request (TEI) disabled
1 Transmit end interrupt request (TEI) enabled
Multiprocessor Interrupt Enable
0 Multiprocessor interrupt request disabled (normal receive operation)
[Clearing condition]
When data is received in which the multiprocessor bit is set to 1
1 Multiprocessor interrupt request enabled
The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the
RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with
the multiprocessor bit set to 1 is received.
Receive Enable
0 Receive operation disabled (RXD
1 Receive operation enabled (RXD
Transmit Enable
0 Transmit operation disabled (TXD
1 Transmit operation enabled (TXD
Receive Interrupt Enable
0 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit Interrupt Enable
0 Transmit data empty interrupt request (TXI) disabled
1 Transmit data empty interrupt request (TXI) enabled
Rev. 6.00, 08/04, page 550 of 628
6 5
RIE TE
0 0
R/W R/W
Bit 0
CKE0 Communication Mode
Asynchronous
0
Synchronous
Asynchronous
1
Synchronous
Asynchronous
0
Synchronous
Asynchronous
1
Synchronous
pin is I/O port)
32
pin is receive data pin)
32
pin is I/O port)
32
pin is transmit data pin)
32
H'AA
4 3
RE MPIE TEIE
0 0
R/W R/W R/W
Description
Clock Source
Internal clock
Internal clock
Internal clock
Reserved (Do not specify this combination)
External clock
External clock
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)
2 1 0
CKE1 CKE0
0 0 0
R/W R/W
SCK Pin Function
32
I/O port
Serial clock output
Clock output
Clock input
Serial clock input
SCI3