Low-Voltage Detection Counter (Lvdcnt); Clock Stop Register 2 (Ckstpr2) - Renesas H8/38024 Hardware Manual

14.2.3

Low-Voltage Detection Counter (LVDCNT)

Bit 7
CNT7
Initial value 0
Read/Write R
LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE. The
counter increments using φ/4 as the clock source until it overflows by switching from H'FF to
H'00, at which time the OVF bit in the LVDSR register is set to 1, indicating that the on-chip
reference voltage generator has stabilized. If the LVD function is used, it is necessary to stand by
until the counter has overflowed. The initial value of LVDCNT is H'00.
14.2.4

Clock Stop Register 2 (CKSTPR2)

Bit 7
LVDCKSTP
Initial value 1
Read/Write R/W
CKSTPR2 is an 8-bit read/write register. It is used to control the module's module standby mode.
Only the bits relevant to the LVD function are described in this section. Refer to the sections on
the other modules for information about the other bits.
Bit 7—LVD Module Standby Control (LVDCKSTP)
This bit is used to control setting of the LVD function to module standby status and cancellation of
that status.
Bit 7
LVDCKSTP Description
0 Sets LVD to module standby status
1 Cancels LVD module standby status
Note: This bit is implemented on the H8/38124 Group only. On other products it is always read as
1 and cannot be written to.
Rev. 6.00, 08/04, page 430 of 628
6 5
CNT6 CNT5 CNT4
0 0
R R
6 5
— —
PW2CKSTP AECKSTP
1 1
— —
4 3
CNT3 CNT2
0 0
R R
4 3
WDCKSTP PW1CKSTP LDCKSTP
1 1
R/W R/W R/W
2 1 0
CNT1 CNT0
0 0 0
R R R
2 1 0
1 1 1
R/W R/W
(initial value)