Flash Memory Enable Register (Fenr) - Renesas H8/38024 Hardware Manual

Bit 7
PDWND Description
0 When this bit is 0 and a transition is made to the subactive mode, the flash memory
enters the power-down mode.
1 When this bit is 1, the flash memory remains in the normal mode even after a
transition is made to the subactive mode.
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
6.6.5

Flash Memory Enable Register (FENR)

Bit 7
FLSHE
Initial value 0
Read/Write R/W
FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and
FLPWCR.
Bit 7—Flash Memory Control Register Enable (FLSHE)
This bit controls access to the flash memory control registers.
Bit 7
FLSHE Description
0 Flash memory control registers cannot be accessed
1 Flash memory control registers can be accessed
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
Rev. 6.00, 08/04, page 160 of 628
6 5
— —
0 0
— —
4 3
— — —
0 0
— — —
(initial value)
2 1
— —
0 0
— —
(initial value)
0
0