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Bit 1—Event Counter PWM Enable
Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC.
Bit 1
ECPWME
Description
0
AEC PWM halted, IRQAEC selected
1
AEC PWM operation enabled, IRQAEC deselected
Bit 0—Reserved
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
Event Counter Control Register (ECCR)
Bit
ACKH1
Initial value
Read/Write
R/W
ECCR performs counter input clock and IRQAEC/IECPWM control.
Bits 7 and 6—AEC Clock Select H (ACKH1, ACKH0)
Bits 7 and 6 select the clock used by ECH.
Bit 7
Bit 6
ACKH1
ACKH0
0
0
1
1
0
1
7
6
5
ACKH0
ACKL1
0
0
0
R/W
R/W
Description
AEVH pin input
φ/2
φ/4
φ/8
4
3
ACKL0
PWCK2
PWCK1
0
0
R/W
R/W
Rev. 6.00, 08/04, page 307 of 628
(initial value)
2
1
PWCK0
0
0
R/W
R/W
R/W
(initial value)
0
0
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