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10.2.3
Transmit Shift Register (TSR)
Bit
Read/Write
TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR,
and serial data transmission is carried out by sending the data to the TXD
from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is
transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is
not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status
register (SSR)).
TSR cannot be read or written directly by the CPU.
10.2.4
Transmit Data Register (TDR)
Bit
TDR7
Initial value
Read/Write
R/W
TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit
data written in TDR is transferred to TSR, and serial data transmission is started. Continuous
transmission is possible by writing the next transmit data to TDR during TSR serial data
transmission.
TDR can be read or written by the CPU at any time.
TDR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Rev. 6.00, 08/04, page 324 of 628
7
6
5
7
6
5
TDR6
TDR5
1
1
1
R/W
R/W
4
3
4
3
TDR4
TDR3
TDR2
1
1
R/W
R/W
R/W
2
1
0
pin in order, starting
32
2
1
0
TDR1
TDR0
1
1
1
R/W
R/W
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