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SSR—Serial Status Register
Bit
7
TDRE
Initial value
1
R/(W) *
Read/Write
Multiprocessor Bit Transfer
0
1
Multiprocessor Bit Receive
0
Data in which the multiprocessor bit is 0 has been received
1
Data in which the multiprocessor bit is 1 has been received
Transmit End
0
Transmission in progress
[Clearing conditions]
Transmission ended
1
[Setting conditions]
Parity Error
0
Reception in progress or completed normally
[Clearing condition] After reading PER = 1, cleared by writing 0 to PER
A parity error has occurred during reception
1
[Setting condition]
Framing Error
0
Reception in progress or completed normally
[Clearing condition] After reading FER = 1, cleared by writing 0 to FER
A framing error has occurred during reception
1
[Setting condition] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
Overrun Error
Reception in progress or completed
0
[Clearing condition] After reading OER = 1, cleared by writing 0 to OER
1
An overrun error has occurred during reception
[Setting condition] When the next serial reception is completed with RDRF set to 1
Receive Data Register Full
0
There is no receive data in RDR
[Clearing conditions] · After reading RDRF = 1, cleared by writing 0 to RDRF
1
There is receive data in RDR
[Setting condition] When reception ends normally and receive data is transferred from RSR to RDR
Transmit Data Register Empty
0
Transmit data written in TDR has not been transferred to TSR
[Clearing conditions] · After reading TDRE = 1, cleared by writing 0 to TDRE
· When data is written to TDR by an instruction
1
Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR
[Setting conditions] · When bit TE in serial control register3 (SCR3) is cleared to 0
· When data is transferred from TDR to TSR
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00, 08/04, page 552 of 628
6
5
RDRF
OER
0
0
R/(W) *
R/(W) *
A 0 multiprocessor bit is transmitted
A 1 multiprocessor bit is transmitted
· After reading TDRE = 1, cleared by writing 0 to TDRE
· When data is written to TDR by an instruction
· When bit TE in serial control register3 (SCR3) is cleared to 0
· When bit TDRE is set to 1 when the last bit of a transmit character is sent
When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM) in the serial mode register (SMR)
reception, and the stop bit is 0
· When RDR data is read by an instruction
H'AC
4
3
FER
PER
TEND
0
0
R/(W) *
R/(W) *
2
1
0
MPBR
MPBT
1
0
0
R
R
R/W
SCI3
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