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9.2.5
Application Note
When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of
the timer mode register A (TMA) cannot be rewritten.
Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)
of the timer mode register A (TMA).
9.3
Timer C
9.3.1
Overview
Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This
timer has two operation modes, interval and auto reload.
Features
Features of timer C are given below.
• Choice of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/64, φ/16, φ/4, φ
external clock (can be used to count external events).
• An interrupt is requested when the counter overflows.
• Up/down-counter switching is possible by hardware or software.
• Subactive mode or subsleep mode operation is possible when φ
clock, or when an external clock is selected.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Rev. 6.00, 08/04, page 244 of 628
/4) or an
W
/4 is selected as the internal
W
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