Renesas H8/38024 Hardware Manual page 531

Item Symbol
Input pin high t
IH
width
Input pin low t
IL
width
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. These characteristics are given as ranges between minimum and maximum values in
order to account for factors such as temperature, power supply voltage, and variation
among production lots. When designing systems, make sure to give due consideration
to the SPEC range. Please see the Web site for this product for actual performance
data.
Table 16.23 Serial Interface (SCI3) Timing
V = 2.7 V to 5.5 V, AV
CC
Item
Input clock Asynchronous
cycle
Clocked synchronous
Input clock pulse width
Transmit data delay time
(clocked synchronous)
Receive data setup time
(clocked synchronous)
Receive data hold time
(clocked synchronous)
Applicable
Pins Min
IRQ0, IRQ1,
2
IRQAEC,
WKP0 to
WKP7,
AEVL, AEVH 0.5
IRQ0, IRQ1,
2
IRQAEC,
WKP0 to
WKP7,
AEVL, AEVH 0.5
= 2.7 V to 5.5 V, V
CC
Symbol Min
t 4
scyc
6
t 0.4
SCKW
t —
TXD
t 400.0 —
RXS
t 400.0 —
RXH
Values
Typ Max Unit
— — t
cyc
t
subcyc
— — t
OSC
— — t
cyc
t
subcyc
— — t
OSC
= AV = 0.0 V, unless otherwise specified
SS SS
Values
Typ Max Unit
— — t or
cyc
t
subcyc
— —
— 0.6 t
scyc
— 1 t or
cyc
t
subcyc
— ns
— ns
Rev. 6.00, 08/04, page 501 of 628
Reference
Test Condition Figure
Figure 16.3
Figure 16.3
Test Reference
Condition Figure
Figure 16.4
Figure 16.4
Figure 16.5
Figure 16.5
Figure 16.5