Pin Configuration
Table 9.18 shows the asynchronous event counter pin configuration.
Table 9.18 Pin Configuration
Name
Asynchronous event input H
Asynchronous event input L
Event input enable interrupt input IRQAEC
Register Configuration
Table 9.19 shows the register configuration of the asynchronous event counter.
Table 9.19 Asynchronous Event Counter Registers
Name
Event counter PWM compare register H ECPWCRH
Event counter PWM compare register L ECPWCRL
Event counter PWM data register H
Event counter PWM data register L
Input pin edge select register
Event counter control register
Event counter control/status register
Event counter H
Event counter L
Clock stop register 2
Abbr.
I/O
Function
AEVH
Input
Event input pin for input to event counter H
AEVL
Input
Event input pin for input to event counter L
Input
Input pin for interrupt enabling event input
Abbr.
ECPWDRH
ECPWDRL
AEGSR
ECCR
ECCSR
ECH
ECL
CKSTPR2
R/W
Initial Value
R/W
H'FF
R/W
H'FF
W
H'00
W
H'00
R/W
H'00
R/W
H'00
R/W
H'00
R
H'00
R
H'00
R/W
H'FF
Rev. 6.00, 08/04, page 303 of 628
Address
H'FF8C
H'FF8D
H'FF8E
H'FF8F
H'FF92
H'FF94
H'FF95
H'FF96
H'FF97
H'FFFB