Serial Control Register 3 (Scr3) - Renesas H8/38024 Hardware Manual

Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0)
Bits 1 and 0 choose φ/64, φ/16, φw/2, or φ as the clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see section
10.2.8, Bit rate register (BRR).
Bit 1 Bit 0
CKS1 CKS0
0 0
0 1
1 0
1 1
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode. In subactive or subsleep mode, SCI3
can be operated when CPU clock is φw/2 only.
10.2.6

Serial Control Register 3 (SCR3)

Bit
TIE
Initial value
Read/Write R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, module standby or watch mode.
Rev. 6.00, 08/04, page 328 of 628
Description
φ clock
φ w/2 clock *
1
/φ w clock *
φ/16 clock
φ/64 clock
7 6 5
RIE TE
0 0 0
R/W R/W
2
4 3
RE MPIE
0 0
R/W R/W
(initial value)
2 1
TEIE CKE1 CKE0
0 0
R/W R/W R/W
0
0