Control Register (Scr0-3) - Fujitsu MB91150 Series Hardware Manual

CHAPTER 15 UART

15.4.1 Control register (SCR0-3)

The control register (SCR0-3) sets the parity, selects the stop-bit length and data
length, selects the frame data format in mode 1, clears the receive-error flag, and sets
send- and receive-operations to enabled or disabled.
I Control register (SCR0-3)
The configuration of the control register (SCR0-3) is shown below.
Address
ch0:0000_001Eh
ch1:0000_0022h
ch2:0000_0026h
ch3:0000_002Ah
R/W: Read/write enabled
W: Write only
TXE
Send-operation enable bit
0
Send operation is disabled
Send operation is enabled
1
RXE
Receive-operation enable bit
0
Receive operation is disabled
1
Receive operation is enabled
REC Receive-error flag-clear bit
0
Clears the FRE, ORE, and PE flags
Does not change, does not affect
1
other operations
A/D Address/data selection bit
0 Data frame
Address frame
1
0 , 1 : The underline indicates an initial value.
312
Figure 15.4-2 Control register (SCR0-3)
bit15 bit14 bit13 bit12
PEN P SBL
R/W R/W R/W R/W
bit11 bit10 bit9
CL A/D REC RXE
R/W W R/W
CL
Data-length selection bit
0
7 bits
1 8 bits
SBL
Stop-bit length selection bit
0
1-bit length
1 2-bit length
Parity selection bit
P
Only (PEN = 1) is valid when parity
is enabled
0
Even-number parity
1
Odd-number parity
PEN Send-enable bit
0
Without parity
1
With parity
bit8 bit7 ............... bit0
TXE (SMR)
R/W
Initial value 00000100
B