Control Register (Scr0/1); Fig. 12.4 Control Register (Scr0/1) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

12.4.1 Control Register (SCR0/1)

The control register (SCR0/1) performs the following: setting parity, selecting stop bit length and data length,
selecting frame data format in mode 1, clearing receive error flag, and enabling/disabling of
transmitting/receiving.
n Control register (SCR0/1)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
CH0: 000035
H
PEN
CH1: 000039
H
R/W R/W
R/W : Both read and write
W : Write only
: Initial value
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
P SBL CL A/D
R/W R/W R/W

Fig. 12.4 Control Register (SCR0/1)

bit 9 bit 8 bit 7.................................. bit 0
REC RXE TXE
W R/W R/W
TXE
0 Disables transmitting
1 Enables transmitting
RXE
0 Disables receiving
Enables receiving
1
REC
0 Clears FRE, ORE, and PE flags
1 Does not change this bit and has no affect on others
A/D
0 Data frame
Address frame
1
CL
0 7 bits
1 8 bits
SBL
0 1-bit length
2-bit length
1
P
Enabled only when Parity Provided (PEN = 1)
0 Even parity
1 Odd parity
PEN
No parity
0
1 With parity
12-10
(SMR)
Transmit Enable Bit
Receive Enable Bit
Receive Error Flag Clear Bit
Address/Data Select Bit
Data-length Select Bit
Stop-bit Length Select Bit
Parity Select Bit
Parity Enable Bit
Initial value
00000100
B