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• High-speed operation
All frequently-used instructions execute in one or two states
Maximum clock rate
8/16/32-bit register-register add/subtract : 40 ns
8 × 8-bit register-register multiply
16 ÷ 8-bit register-register divide
16 × 16-bit register-register multiply
32 ÷ 16-bit register-register divide
• Two CPU operating modes
Normal mode*
Advanced mode
Note: * Not available in the H8S/2633 Series.
• Power-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
2.1.2
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions is different in each
CPU.
Instruction
MULXU
MULXS
22
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
: 25 MHz
: 120 ns
: 480 ns
: 160 ns
: 800 ns
Execution States
H8S/2600
3
4
4
5
H8S/2000
12
20
13
21
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