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Table 1-1
Overview
Item
CPU
Bus controller
PC break controller •
DMA controller
(DMAC)
2
Specification
•
General-register machine
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
•
High-speed operation suitable for realtime control
Maximum clock rate: 25 MHz
High-speed arithmetic operations
8/16/32-bit register-register add/subtract : 40 ns
16 × 16-bit register-register multiply
16 × 16 + 42-bit multiply and accumulate : 160 ns
32 ÷ 16-bit register-register divide
•
Instruction set suitable for high-speed operation
Sixty-nine basic instructions
8/16/32-bit move/arithmetic and logic instructions
Unsigned/signed multiply and divide instructions
Multiply-and accumulate instruction
Powerful bit-manipulation instructions
•
Two CPU operating modes
Normal mode: 64-kbyte address space
(cannot be used in the H8S/2633 Series)
Advanced mode: 16-Mbyte address space
•
Address space divided into 8 areas, with bus specifications settable
independently for each area
•
Choice of 8-bit or 16-bit access space for each area
•
2-state or 3-state access space can be designated for each area
•
Number of program wait states can be set for each area
•
Burst ROM directly connectable
•
Possible to connect a maximum of 8 MB of DRAM (alternatively, it is also
possible to use an interval timer)
•
External bus release function
Supports debugging functions by means of PC break interrupts
•
Two break channels
•
Short address mode and full address mode selectable
•
Short address mode: 4 channels
Full address mode: 2 channels
•
Transfer possible in repeat mode/block transfer mode
Transfer possible in single address mode
•
Activation by internal interrupt possible
: 160 ns
: 800 ns
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