Hitachi H8S/2633 Hardware Manual page 5

5.3.3 Interrupt Exception Handling Vector Table Table 5-4 Interrupt Sources, Vector

5.4.2 Interrupt Control Mode 0

7.10.4 Transition Timing

8.1.3 Overview of Functions

8.7 Usage Notes

9.1.2 Block Diagram

9.3.3 DTC Vector Table

10.1 Overview

10.3.3 Pin Functions

10.7.1 Overview

10.8.1 Overview

(See Manual for Details)

Addresses, and Interrupt Priorities

8-bit timer channel names amended

Figure 5-5 Flowchart of Procedure

Up to Interrupt Acceptance in

Interrupt Control Mode 0 amended

Figure 7-30 DACK Output Timing

when DDS=1 (Example Showing

DRAM Access)

Figure 7-31 DACK Output Timing

when DDS=0 (Example Showing

DRAM Access)

Figure 7-39 Bus-Released State

Transition Timing amended

Table 8-1 Overview of DMAC

SCI transfer source names

DMAC Register Access during

Operation added

Figure 8-40 and figure 8-41 added

Figure 9-1 Block Diagram of DTC

Table 9-4 Interrupt Sources, DTC

Vector Addresses, and

Corresponding DTCEs

8-bit timer channel names amended

Capacitance load value amended

Table 10-1 Port Functions

Table 10-5 Port 3 Pin Functions

Figure 10-6 Port A Pin Functions

Figure 10-9 Port B Pin Functions