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6.3.4
Operation in Transitions to Power-Down Modes ................................................. 126
6.3.5
PC Break Operation in Continuous Data Transfer ............................................... 127
6.3.6
When Instruction Execution is Delayed by One State.......................................... 128
6.3.7
Additional Notes ................................................................................................... 129
Section 7
Bus Controller
7.1
Overview............................................................................................................................ 131
7.1.1
Features ................................................................................................................. 131
7.1.2
Block Diagram...................................................................................................... 133
7.1.3
Pin Configuration.................................................................................................. 134
7.1.4
Register Configuration.......................................................................................... 135
7.2
Register Descriptions ......................................................................................................... 136
7.2.1
Bus Width Control Register (ABWCR) ............................................................... 136
7.2.2
Access State Control Register (ASTCR).............................................................. 137
7.2.3
Wait Control Registers H and L (WCRH, WCRL) .............................................. 138
7.2.4
Bus Control Register H (BCRH) .......................................................................... 142
7.2.5
Bus Control Register L (BCRL) ........................................................................... 144
7.2.6
Pin Function Control Register (PFCR) ................................................................. 146
7.2.7
Memory Control Register (MCR) ........................................................................ 149
7.2.8
DRAM Control Register (DRAMCR).................................................................. 151
7.2.9
Refresh Timer Counter (RTCNT) ........................................................................ 153
7.2.10 Refresh Time Constant Register (RTCOR).......................................................... 153
7.3
Overview of Bus Control ................................................................................................... 154
7.3.1
Area Partitioning................................................................................................... 154
7.3.2
Bus Specifications ................................................................................................ 155
7.3.3
Memory Interfaces................................................................................................ 156
7.3.4
Interface Specifications for Each Area ................................................................. 157
7.3.5
Chip Select Signals ............................................................................................... 158
7.4
Basic Bus Interface ............................................................................................................ 159
7.4.1
Overview............................................................................................................... 159
7.4.2
Data Size and Data Alignment.............................................................................. 159
7.4.3
Valid Strobes ........................................................................................................ 161
7.4.4
Basic Timing......................................................................................................... 162
7.4.5
Wait Control.......................................................................................................... 170
7.5
DRAM Interface ................................................................................................................ 172
7.5.1
Overview............................................................................................................... 172
7.5.2
Setting up DRAM Space ...................................................................................... 172
7.5.3
Address Multiplexing............................................................................................ 173
7.5.4
Data Bus................................................................................................................ 173
7.5.5
DRAM Interface Pins ........................................................................................... 174
7.5.6
Basic Timing......................................................................................................... 174
7.5.7
Precharge State Control ........................................................................................ 176
7.5.8
Wait Control.......................................................................................................... 177
iv
.................................................................................................. 131
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